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Department of Computer Science and Technology

Friday, 21 June, 2024 - 11:00 to 12:00
Daniel Lo, Microsoft Research
Lecture Theatre 2, Department of Computer Science & Technology, 15 JJ Thompson Avenue, Madingley Road, Cambridge, CB3 0FD

Digital systems are growing in importance and computing hardware is growing more heterogeneous. Hardware design, however, remains laborious and expensive, in part due to the limitations of conventional hardware description languages (HDLs) like VHDL and Verilog. A longstanding research goal has been programming hardware like software, with high-level languages that can generate efficient hardware designs. In this talk, we will present Kanagawa, a language that takes a new approach to combine the programmer productivity benefits of traditional High-Level Synthesis (HLS) approaches with the expressibility and hardware efficiency of Register-Transfer Level (RTL) design. The language's concise syntax, matched with a hardware design-friendly execution model, permits a relatively simple toolchain to map high-level code into efficient hardware implementations.
Seminar series: 
Computer Architecture Group Meeting