- Professor of Computer Engineering
Biography
Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Professor Moore is the senior member of the Computer Architecture research group.
The primary focus of Simon's research is the CHERI secure processor which is part of a full-stack security project that includes RISC-V cores with CHERI security extensions and a complete software stack including compiler/linker and full OS. Key components have been formally verified. CHERI is in an industrial evaluation and transition phase with substantial funding under the Innovate UK Digital Security by Design programme.
Simon has substantial experience of mentoring Ph.D. students having been the primary supervisor for over 25 students including Dr Daniel Greenfield who won the UK Distinguished Dissertation prize in Computer Science for his work on Communication Locality in Computation: Software, Chip Multiprocessors and Brains. Simon is always looking for new Ph.D. students to join his team: see Future Research Opportunities
Simon is also a Fellow and Director of Studies at Trinity Hall, one of the colleges associated with the University of Cambridge. I mentor undergraduates and undertake admission in Computer Science.
Themes
Professional Activities
For a list of professional activities, please see my resume
Recent News
For recent news and more up-to-date information, please see my personal homepage
Publications
Please see the publications page of my resume for a complete list of publications.
Some recent publications
Naylor M, Moore S, Mokhov A, Thomas D, Beaumont J, Fleming S, Markettos AT, Bytheway T, Brown A. Termination detection for fine-grained message-passing architectures In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors, 6-8 July 2020. PDF Talk
Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, and Robert N. M. Watson. Cornucopia: Temporal Safety for CHERI Heaps. In Proceedings of the 41st IEEE Symposium on Security and Privacy (Oakland 2020). San Jose, CA, USA, May 18-20, 2020. PDF Talk
Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, and Peter Sewell. Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. In Proceedings of the 41st IEEE Symposium on Security and Privacy ("Oakland"), May 2020. PDF
Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, and Timothy M. Jones. CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (IEEE MICRO 2019). Columbus, Ohio, USA, October 12-16, 2019. PDF DIO: 10.1145/3352460.3358288
Matthew Naylor, Simon W. Moore, David Thomas. Tinsel: a manythread overlay for FPGA clusters. International Conference on Field Programmable Logic and Applications (FPL) 9-13 September, 2019. (Open Access) DIO: 10.1109/FPL.2019.00066
Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, James Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, and Jonathan Woodruff. CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. In Proceedings of 2019 Architectural Support for Programming Languages and Operating Systems (ASPLOS’19). Providence, RI, USA, April 13-17, 2019 (PDF) DOI: 10.1145/3297858.3304042 Won the best paper prize
A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson. Thunderclap: Exploring Vulnerabilities in Operating-System IOMMU Protection from Untrustworthy Peripherals. 2019 NDSS Symposium (Network and Distributed System Security), San Diego, 24-27 February 2019 (PDF, Website) DOI: 10.14722/ndss.2019.23194
Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, MichaelRoe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore, and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices. Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD). Orlando, FL, USA, October 7-10, 2018. (PDF) DOI: 10.1109/ICCD.2018.00023
Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W Moore, Alex Bradbury, Hongyan Xia, Robert NM Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey Son, A Theodore Markettos. Efficient Tagged Memory. IEEE 35th International Conference on Computer Design (ICCD), 2017 (PDF) DOI: 10.1109/ICCD.2017.112
David Chisnall, Brooks David, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert Norton, Stacey Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N.M. Watson. CHERI JNI: Sinking the Java security model into the C. Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017, Pages 569-583. (PDF Open Access) DOI: 10.1145/3037697.3037725
Matthew Naylor, Simon W. Moore and Alan Mujumdar, A Consistency Checker for Memory Subsystem Traces, International Conference on Formal Methods in Computer-Aided Design (FMCAD), supported by IEEE & ACM, Mountain View, CA, USA, October 3-6, 2016. (PDF) DOI: 10.1109/FMCAD.2016.7886671
Matthew Naylor and Simon W. Moore, A generic synthesisable test bench, 13th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 21-23 September 2015, Austin, TX, USA, pp 128-137. (PDF) DOI: 10.1109/MEMCOD.2015.7340479
Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert Norton, Michael Roe, Stacey Son, Munraj Vadera, CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization, IEEE Symposium on Security and Privacy (aka Oakland), May 2015. (PDF) DOI: 10.1109/SP.2015.9
David Chisnall, Colin Rothwell, Brooks Davis, Robert N.M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Peter G. Neumann and Michael Roe. Beyond the PDP-11: Processor support for a memory-safe C abstract machine. Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, ACM, 2015. (PDF) Won the audience picks: best presentation award
Matthew Naylor and Simon W. Moore, Rapid codesign of a soft vector processor and its compiler, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)