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Department of Computer Science and Technology

  • Professor of Computer Engineering

Biography

Simon Moore is a Professor of Computer Engineering at the University of Cambridge Department of Computer Science and Technology (previously the Computer Laboratory) in England, where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Professor Moore is the senior member of the Computer Architecture research group.

The primary focus of Simon's research is the CHERI secure processor which is part of a full-stack security project that includes RISC-V cores with CHERI security extensions and a complete software stack including compiler/linker and full OS. Key components have been formally verified. CHERI is in an industrial evaluation and transition phase with substantial funding under the Innovate UK Digital Security by Design programme.

Simon has substantial experience of mentoring Ph.D. students having been the primary supervisor for over 25 students including Dr Daniel Greenfield who won the UK Distinguished Dissertation prize in Computer Science for his work on Communication Locality in Computation: Software, Chip Multiprocessors and Brains. Simon is always looking for new Ph.D. students to join his team: see Future Research Opportunities

Simon is also a Fellow and Director of Studies at Trinity Hall, one of the colleges associated with the University of Cambridge. I mentor undergraduates and undertake admission in Computer Science.

Professional Activities

For a list of professional activities, please see my resume

Recent news

Publications

Please see the publications page of my resume for a complete list of publications.

Some recent publications

Naylor M, Moore S, Mokhov A, Thomas D, Beaumont J, Fleming S, Markettos AT, Bytheway T, Brown A. Termination detection for fine-grained message-passing architectures In Proceedings of the 31st IEEE International Conference on Application-specific Systems, Architectures and Processors, 6-8 July 2020. PDF  Talk

Nathaniel Wesley Filardo, Brett F. Gutstein, Jonathan Woodruff, Sam Ainsworth, Lucian Paul-Trifu, Brooks Davis, Hongyan Xia, Edward Tomasz Napierala, Alexander Richardson, John Baldwin, David Chisnall, Jessica Clarke, Khilan Gudka, Alexandre Joannou, A. Theodore Markettos, Alfredo Mazzinghi, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, Timothy M. Jones, Simon W. Moore, Peter G. Neumann, and Robert N. M. Watson. Cornucopia: Temporal Safety for CHERI Heaps. In Proceedings of the 41st IEEE Symposium on Security and Privacy (Oakland 2020). San Jose, CA, USA, May 18-20, 2020. PDF  Talk

Kyndylan Nienhuis, Alexandre Joannou, Thomas Bauereiss, Anthony Fox, Michael Roe, Brian Campbell, Matthew Naylor, Robert M. Norton, Simon W. Moore, Peter G. Neumann, Ian Stark, Robert N. M. Watson, and Peter Sewell. Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process. In Proceedings of the 41st IEEE Symposium on Security and Privacy ("Oakland"), May 2020. PDF

Hongyan Xia, Jonathan Woodruff, Sam Ainsworth, Nathaniel W. Filardo, Michael Roe, Alexander Richardson, Peter Rugg, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson, and Timothy M. Jones. CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. In Proceedings of the 52nd IEEE/ACM International Symposium on Microarchitecture (IEEE MICRO 2019). Columbus, Ohio, USA, October 12-16, 2019. PDF DIO: 10.1145/3352460.3358288

Matthew Naylor, Simon W. Moore, David Thomas. Tinsel: a manythread overlay for FPGA clusters. International Conference on Field Programmable Logic and Applications (FPL) 9-13 September, 2019. (Open Access) DIO: 10.1109/FPL.2019.00066

Brooks Davis, Robert N. M. Watson, Alexander Richardson, Peter G. Neumann, Simon W. Moore, John Baldwin, David Chisnall, James Clarke, Nathaniel Wesley Filardo, Khilan Gudka, Alexandre Joannou, Ben Laurie, A. Theodore Markettos, J. Edward Maste, Alfredo Mazzinghi, Edward Tomasz Napierala, Robert M. Norton, Michael Roe, Peter Sewell, Stacey Son, and Jonathan Woodruff. CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment. In Proceedings of 2019 Architectural Support for Programming Languages and Operating Systems (ASPLOS’19). Providence, RI, USA, April 13-17, 2019 (PDF) DOI: 10.1145/3297858.3304042 Won the best paper prize

A. Theodore Markettos, Colin Rothwell, Brett F. Gutstein, Allison Pearce, Peter G. Neumann, Simon W. Moore, Robert N. M. Watson. Thunderclap: Exploring Vulnerabilities in Operating-System IOMMU Protection from Untrustworthy Peripherals. 2019 NDSS Symposium (Network and Distributed System Security), San Diego, 24-27 February 2019 (PDF, Website) DOI: 10.14722/ndss.2019.23194

Hongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, MichaelRoe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alex Richardson, Simon W. Moore, and Robert N. M. Watson. CheriRTOS: A Capability Model for Embedded Devices. Proceedings of the 2018 IEEE 36th International Conference on Computer Design (ICCD). Orlando, FL, USA, October 7-10, 2018. (PDF) DOI: 10.1109/ICCD.2018.00023

Alexandre Joannou, Jonathan Woodruff, Robert Kovacsics, Simon W Moore, Alex Bradbury, Hongyan Xia, Robert NM Watson, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G Neumann, Alfredo Mazzinghi, Alex Richardson, Stacey Son, A Theodore Markettos. Efficient Tagged Memory. IEEE 35th International Conference on Computer Design (ICCD), 2017 (PDF) DOI: 10.1109/ICCD.2017.112

David Chisnall, Brooks David, Khilan Gudka, David Brazdil, Alexandre Joannou, Jonathan Woodruff, A. Theodore Markettos, J. Edward Maste, Robert Norton, Stacey Son, Michael Roe, Simon W. Moore, Peter G. Neumann, Ben Laurie, Robert N.M. Watson. CHERI JNI: Sinking the Java security model into the C. Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2017, Pages 569-583. (PDF Open Access) DOI: 10.1145/3037697.3037725

Matthew Naylor, Simon W. Moore and Alan Mujumdar, A Consistency Checker for Memory Subsystem Traces, International Conference on Formal Methods in Computer-Aided Design (FMCAD), supported by IEEE & ACM, Mountain View, CA, USA, October 3-6, 2016. (PDF) DOI: 10.1109/FMCAD.2016.7886671

Matthew Naylor and Simon W. Moore, A generic synthesisable test bench, 13th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), 21-23 September 2015, Austin, TX, USA, pp 128-137. (PDF) DOI: 10.1109/MEMCOD.2015.7340479

Robert N. M. Watson, Jonathan Woodruff, Peter G. Neumann, Simon W. Moore, Jonathan Anderson, David Chisnall, Nirav Dave, Brooks Davis, Khilan Gudka, Ben Laurie, Steven J. Murdoch, Robert Norton, Michael Roe, Stacey Son, Munraj Vadera, CHERI: A Hybrid Capability-System Architecture for Scalable Software Compartmentalization, IEEE Symposium on Security and Privacy (aka Oakland), May 2015. (PDF) DOI: 10.1109/SP.2015.9

David Chisnall, Colin Rothwell, Brooks Davis, Robert N.M. Watson, Jonathan Woodruff, Munraj Vadera, Simon W. Moore, Peter G. Neumann and Michael Roe. Beyond the PDP-11: Processor support for a memory-safe C abstract machine. Proceedings of the Fifteenth Edition of ASPLOS on Architectural Support for Programming Languages and Operating Systems, ACM, 2015. (PDF) Won the audience picks: best presentation award

Matthew Naylor and Simon W. Moore, Rapid codesign of a soft vector processor and its compiler, 24th International Conference on Field Programmable Logic and Applications (FPL2014), 2-4 September 2014. (PDF)

Conference proceedings

  • Naylor, M., Moore, S., Mokhov, A., Thomas, D., Beaumont, J., Fleming, S., Markettos, AT., Bytheway, T. and Brown, A., 2020. Termination detection for fine-grained message-passing architectures 2020 IEEE 31st International Conference on Application-specific Systems, Architectures and Processors (ASAP),
    Doi: 10.1109/ASAP49362.2020.00012
  • Van Der Maas, M. and Moore, SW., 2020. Protecting Enclaves from Intra-Core Side-Channel Attacks through Physical Isolation CYSARM 2020 - Proceedings of the 2nd Workshop on Cyber-Security Arms Race,
    Doi: http://doi.org/10.1145/3411505.3418437
  • Chisnall, D., Davis, B., Gudka, K., Brazdil, D., Joannou, A., Woodruff, J., Markettos, AT., Maste, JE., Norton, R., Son, S., Roe, M., Moore, SW., Neumann, PG., Laurie, B. and Watson, RNM., 2017. CHERI JNI: Sinking the Java Security Model into the C OPERATING SYSTEMS REVIEW, v. 51
    Doi: 10.1145/3037697.3037725
  • Tarawneh, G., Mokhov, A., Naylor, M., Rast, A., Moore, SW., Thomas, DB., Yakovlev, A. and Brown, A., 2017. Programming Model to Develop Supercomputer Combinatorial Solvers Proceedings of the International Conference on Parallel Processing Workshops,
    Doi: http://doi.org/10.1109/ICPPW.2017.35
  • Naylor, MF., Moore, S. and Mujumdar, A., 2016. A Consistency Checker for Memory Subsystem Traces Formal Methods in Computer-Aided Design,
  • Chisnall, D., Rothwell, C., Watson, RNM., Woodruff, J., Vadera, M., Moore, SW., Roe, M., Davis, B. and Neumann, PG., 2015. Beyond the PDP-11: Architectural support for a memory-safe C abstract machine Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems,
    Doi: http://doi.org/10.1145/2694344.2694367
  • Watson, RNM., Woodruff, J., Neumann, PG., Moore, SW., Anderson, J., Chisnall, D., Dave, N., Davis, B., Gudka, K., Laurie, B., Murdoch, SJ., Norton, R., Roe, M., Son, S. and Vadera, M., 2015. CHERI: A hybrid capability-system architecture for scalable software compartmentalization Proceedings - IEEE Symposium on Security and Privacy, v. 2015-July
    Doi: 10.1109/SP.2015.9
  • Naylor, M. and Moore, S., 2015. A generic synthesisable test bench 2015 ACM/IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE 2015,
    Doi: 10.1109/MEMCOD.2015.7340479
  • Fox, PJ., Markettos, AT. and Moore, SW., 2014. Reliably prototyping large SoCs using FPGA clusters 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014,
    Doi: 10.1109/ReCoSoC.2014.6861350
  • Markettos, AT., Fox, PJ., Moore, SW. and Moore, AW., 2014. Interconnect for commodity FPGA clusters: Standardized or customized? Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014,
    Doi: 10.1109/FPL.2014.6927472
  • Naylor, M. and Moore, SW., 2014. Rapid codesign of a soft vector processor and its compiler Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014,
    Doi: 10.1109/FPL.2014.6927425
  • Naylor, M., Fox, PJ., Markettos, AT. and Moore, SW., 2013. Managing the FPGA memory wall: Custom computing or vector processing? 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings,
    Doi: 10.1109/FPL.2013.6645538
  • Woodruff, J., Moore, SW. and Watson, RNM., 2013. Memory segmentation to support secure applications CEUR Workshop Proceedings, v. 965
  • Moore, SW., Fox, PJ., Marsh, SJT., Markettos, AT. and Mujumdar, A., 2012. Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012,
    Doi: 10.1109/FCCM.2012.32
  • Watts, PM., Barrow-Williams, N. and Moore, SW., 2011. Requirements of low power photonic networks for distributed shared memory computers Optics InfoBase Conference Papers,
    Doi: http://doi.org/10.1364/ofc.2011.othq5
  • Barrow-Williams, N., Fensch, C. and Moore, S., 2010. Proximity coherence for chip multiprocessors Proceedings of the 19th international conference on Parallel architectures and compilation techniques,
  • Barrow-Williams, N., Fensch, C. and Moore, S., 2009. A Communication Characterisation of Splash-2 and Parsec PROCEEDINGS OF THE 2009 IEEE INTERNATIONAL SYMPOSIUM ON WORKLOAD CHARACTERIZATION,
  • Banerjee, A., Wolkotte, PT., Mullins, RD., Moore, SW. and Smit, GJM., 2009. An Energy and Performance Exploration of Network-on-Chip Architectures IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v. 17
    Doi: http://doi.org/10.1109/TVLSI.2008.2011232
  • Banerjee, A. and Moore, SW., 2009. Flow-Aware Allocation for On-Chip Networks 2009 3RD ACM/IEEE INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP,
  • Markettos, AT. and Moore, SW., 2009. The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2009, PROCEEDINGS, v. 5747
  • Greenfield, DL. and Moore, SW., 2008. Fractal Communication in Software Data Dependency Graphs SPAA'08: PROCEEDINGS OF THE TWENTIETH ANNUAL SYMPOSIUM ON PARALLELISM IN ALGORITHMS AND ARCHITECTURES,
  • Kinniment, D., Koelmans, A., Fei, X., Bystrov, A., Chester, G., Carloni, L., Russell, G., Roncken, M., Vivet, P., Murali, S., Clark, I., Moore, S., Yakovlev, A., Bainbridge, J., Bertozzi, D. and Goossens, K., 2008. Message from the chairs Proceedings - Second IEEE International Symposium on Networks-on-Chip, NOCS 2008,
    Doi: http://doi.org/10.1109/NOCS.2008.4492714
  • Francis, R., 2008. A network of time-division multiplexed wiring for FPGAs
  • Banerjee, A., Mullins, R. and Moore, S., 2007. A power and energy exploration of Network-on-Chip architectures NOCS 2007: First International Symposium on Networks-on-Chip, Proceedings,
  • Hollis, S. and Moore, SW., 2007. RasP: An area-efficient, on-chip network PROCEEDINGS 2006 INTERNATIONAL CONFERENCE ON COMPUTER DESIGN,
  • Mullins, R., Moore, S. and IEEE, , 2007. Demystifying data-driven and pausible clocking schemes ASYNC 2007: 13TH IEEE INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS,
  • Greenfield, D., Banerjee, A., Lee, JG. and Moore, S., 2007. Implications of Rent's rule for NoC design and its fault-tolerance NOCS 2007: FIRST INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP, PROCEEDINGS,
  • Taylor, K. and Moore, S., 2006. My compiler really understands me: An adaptive programming language tutor ADAPTIVE HYPERMEDIA AND ADAPTIVE WEB-BASED SYSTEMS, PROCEEDINGS, v. 4018
  • Oikonomakos, P., Fournier, J. and Moore, S., 2006. Implementing cryptography on TFT technology for secure display applications SMART CARD RESEARCH AND ADVANCED APPLICATIONS, PROCEEDINGS, v. 3928
  • Hollis, S. and Moore, SW., 2006. An area-efficient, pulse-based interconnect 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS,
  • Li, HY., Markettos, AT. and Moore, S., 2005. A security evaluation methodology for smart cards against electromagnetic analysis 39TH ANNUAL 2005 INTERNATIONAL CARNAHAN CONFERENCE ON SECURITY TECHNOLOGY, PROCEEDINGS,
  • Li, HY., Markettos, AT. and Moore, S., 2005. Security evaluation against electromagnetic analysis at design time HLDVT'05: TENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS,
  • Roberts, GF., Penty, RV., White, IH., West, A. and Moore, S., 2005. Multi-wavelength data encoding for improved input power dynamic range in semiconductor optical amplifier switches Proceedings of the 18th Annual Meeting of the IEEE Lasers and Electro-optics Society,
    Doi: http://doi.org/10.1109/LEOS.2005.1548219
  • Hollis, S. and Moore, SW., 2005. An asynchronous interconnect architecture for device security enhancement 19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS,
  • Li, HY., Markettos, AT. and Moore, S., 2005. Security evaluation against electromagnetic analysis at design time CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, v. 3659
  • Moore, S., Anderson, R., Mullins, R., Taylor, G. and Fournier, JJA., 2003. Balanced self-checking asynchronous logic for smart card applications MICROPROCESSORS AND MICROSYSTEMS, v. 27
    Doi: 10.1016/S0141-9331(03)00092-9
  • Fournier, JJA., Moore, S., Li, HY., Mullins, R. and Taylor, G., 2003. Security evaluation of asynchronous circuits CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS CHES 2003, PROCEEDINGS, v. 2779
  • Moore, S., Taylor, G., Mullins, R. and Robinson, P., 2002. Point to point GALS interconnect ASYNC: EIGHTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS,
  • Moore, S., Anderson, R., Cunningham, P., Mullins, R. and Taylor, G., 2002. Improving smart card security using self-timed circuits ASYNC: EIGHTH INTERNATIONAL SYMPOSIUM ON ASYNCHRONOUS CIRCUITS AND SYSTEMS, PROCEEDINGS,
  • Moore, S., 2001. Protecting consumer security devices: The next 10 years Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), v. 2140
    Doi: 10.1007/3-540-45418-7_1
  • Moore, SW., Taylor, GS., Cunningham, PA., Mullins, RD. and Robinson, P., 2000. Self calibrating clocks for globally asynchronous locally synchronous systems 2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS,
  • Moore, SW. and Robinson, P., 1998. Rapid prototyping of self-timed circuits INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS,
  • Nienhuis, K., Joannou, A., Bauereiss, T., Fox, A., Roe, M., Campbell, B., Naylor, M., Norton, RM., Moore, SW., Neumann, PG., Stark, I., Watson, R. and Sewell, P., Rigorous engineering for hardware security: Formal modelling and proof in the CHERI design and implementation process 2020 IEEE Symposium on Security and Privacy (SP),
  • Chisnall, DT., Davis, B., Gudka, K., Brazdil, D., Joannou, A., Woodruff, J., Markettos, AT., Maste, JE., Norton, R., Son, S., Roe, M., Moore, SW., Neumann, PG., Laurie, B. and Watson, RNM., CHERI JNI: Sinking the Java security model into the C Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems,
  • Filardo, N., Gutstein, BF., Woodruff, J., Ainsworth, S., Paul-Trifu, L., Davis, B., Xia, H., Napierala, ET., Richardson, A., Baldwin, J., Chisnall, D., Clarke, J., Gudka, K., Joannou, A., Markettos, AT., Mazzinghi, A., Norton, RM., Roe, M., Sewell, P., Son, S., Jones, TM., Moore, SW., Neumann, PG. and Watson, RNM., Cornucopia: Temporal Safety for CHERI Heaps Proceedings of the 41st IEEE Symposium on Security and Privacy,
  • Woodruff, JD., Joannou, A., Kovacsics, R., Moore, SW., Bradbury, A., Xia, H., Robert, RNM., Chisnall, D., Roe, M., Davis, B., Napierala, E., Baldwin, J., Gudka, K., Neumann, PG., Mazzinghi, A., Richardson, A., Son, S. and Markettos, AT., Efficient Tagged Memory IEEE International Conference on Computer Design - VLSI in Computers and Processors,
  • Naylor, M., Moore, SW., Thomas, D., Beaumont, JR., Fleming, S., Vousden, M., Markettos, AT., Bytheway, T. and Brown, A., General hardware multicasting for fine-grained message-passing architectures
  • Xia, H., Woodruff, J., Barral, H., Esswood, L., Joannou, A., Kovacsics, R., Chisnall, D., Roe, M., Davis, B., Napierala, E., Baldwin, J., Gudka, K., Neumann, PG., Richardson, A., Moore, S. and Watson, R., CheriRTOS: A Capability Model for Embedded Devices
  • Markettos, AT., Rothwell, C., Gutstein, BF., Pearce, A., Neumann, PG., Moore, SW. and Watson, RNM., Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals
    Doi: 10.14722/ndss.2019.23194
  • David, B., Watson, R., Alexander, R., Peter, N., Moore, S., Baldwin, J., Chisnall, D., Clarke, J., Filardo, N., Gudka, K., Joannou, A., Laurie, B., Markettos, A., Maste, J., Mazzinghi, A., Napierala, E., Norton, R., Roe, M., Sewell, P., Son, S. and Woodruff, J., CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment ACM,
  • Naylor, M., Moore, S. and Thomas, D., Tinsel: a manythread overlay for FPGA clusters 2019 29th International Conference on Field Programmable Logic and Applications (FPL),
    Doi: http://doi.org/10.1109/FPL.2019.00066
  • Xia, H., Woodruff, J., Ainsworth, S., Filardo, N., Roe, M., Richardson, A., Rugg, P., Neumann, P., Moore, S., Watson, R. and Jones, T., CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety
  • Journal articles

  • Markettos, AT., Watson, RNM., Moore, SW., Sewell, P. and Neumann, PG., 2019. Inside risks through computer architecture, Darkly Communications of the ACM, v. 62
    Doi: 10.1145/3325284
  • Watson, RNM., Norton, RM., Woodruff, J., Moore, SW., Neumann, PG., Anderson, J., Chisnall, D., Davis, B., Laurie, B., Roe, M., Dave, NH., Gudka, K., Joannou, A., Markettos, AT., Maste, E., Murdoch, SJ., Rothwell, C., Son, SD. and Vadera, M., 2016. Fast Protection-Domain Crossing in the CHERI Capability-System Architecture IEEE Micro, v. 36
    Doi: 10.1109/MM.2016.84
  • Woodruff, J., Watson, RNM., Chisnall, D., Moore, SW., Anderson, J., Davis, B., Laurie, B., Neumann, PG., Norton, R. and Roe, M., 2014. The CHERI capability model: Revisiting RISC in an age of risk Proceedings - International Symposium on Computer Architecture, v. 42
    Doi: http://doi.org/10.1109/ISCA.2014.6853201
  • Audzevich, Y., Watts, PM., West, A., Mujumdar, A., Moore, SW. and Moore, AW., 2013. Power Optimized Transceivers for Future Switched Networks IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v. PP
    Doi: 10.1109/TVLSI.2013.2283300
  • Chadwick, GA. and Moore, SW., 2012. Mamba: A scalable communication centric multi-threaded processor architecture Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors,
    Doi: http://doi.org/10.1109/ICCD.2012.6378652
  • Watts, PM., Moore, SW. and Moore, AW., 2012. Energy implications of photonic networks with speculative transmission Journal of Optical Communications and Networking, v. 4
    Doi: 10.1364/JOCN.4.000503
  • Watts, PM., Barrow-Williams, N. and Moore, SW., 2011. Requirements of low power photonic networks for distributed shared memory computers Optics InfoBase Conference Papers,
  • Watts, PM., Barrow-Williams, N. and Moore, SW., 2011. Requirements of low power photonic networks for distributed shared memory computers 2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference, OFC/NFOEC 2011,
  • Bassett, DS., Greenfield, DL., Meyer-Lindenberg, A., Weinberger, DR., Moore, SW. and Bullmore, ET., 2010. Efficient Physical Embedding of Topologically Complex Information Processing Networks in Brains and Computer Circuits PLOS COMPUT BIOL, v. 6
    Doi: http://doi.org/10.1371/journal.pcbi.1000748
  • Greenfield, S., 2009. Implications of electronics technology trends for algorithm design Computer Journal, v. 52
  • Greenfield, DL. and Moore, SW., 2008. Brief announcement: Fractal communication in software data dependency graphs Annual ACM Symposium on Parallelism in Algorithms and Architectures,
    Doi: http://doi.org/10.1145/1378533.1378555
  • Oikonomakos, P., Paul, PC., Moore, SW., Tam, SWB. and Ebihara, H., 2007. Dynamic-logic PLA on low-temperature polysilicon TFT technology Electronics Letters, v. 43
    Doi: http://doi.org/10.1049/el:20073332
  • Oikonomakos, P., Paul, PC., Moore, SW., Tam, SWB. and Ebihara, H., 2007. Dynamic-logic PLA on low-temperature ELECTRON LETT, v. 43
    Doi: http://doi.org/10.1049/el:20073332
  • Fournier, JJA. and Moore, S., 2006. A vector approach to cryptography implementation LECT NOTES COMPUT SC, v. 3919
  • Fairbanks, S., 2004. Analog micropipeline rings for high precision timing Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems, v. 10
  • Taylor, G., Moore, S., Wilcox, S. and Laboratory, PR., 2000. An on-chip dynamically recalibrated delay line for embedded self-timed systems Proceedings - International Symposium on Asynchronous Circuits and Systems,
    Doi: 10.1109/ASYNC.2000.836786
  • Moore, S., Robinson, P. and Wilcox, S., 1996. Rotary pipeline processors IEE P-COMPUT DIG T, v. 143
  • Moore, SW. and Graham, BT., 1995. Tagged up down sorter - A hardware priority queue COMPUT J, v. 38
  • Woodruff, J., Joannou, A., Xia, H., Davis, B., Neumann, PG., Watson, RNM., Moore, S., Fox, A., Norton, R., Chisnall, D. and Fox, A., CHERI Concentrate: Practical Compressed Capabilities IEEE Transactions on Computers,
    Doi: 10.1109/tc.2019.2914037
  • Mullins, RD., Fensch, C., Barrow-Williams, N. and Moore, SW., Designing a Physical Locality Aware Coherence Protocol for Chip-Multiprocess\ ors IEEE Transactions on Computers,
  • Book chapters

  • Watson, RNM., Neumann, PG. and Moore, SW., 2017. Balancing Disruption and Deployability in the CHERI Instruction-Set Architecture (ISA)
  • Moore, SW., Fox, PJ., Markettos, AT. and Naylor, M., 2015. Custom computing or vector processing?
    Doi: 10.1142/9781783266975_0007
  • Moore, S., 2001. Protecting Consumer Security Devices
    Doi: http://doi.org/10.1007/3-540-45418-7_1
  • Datasets

  • Filardo, N., Gutstein, B., Woodruff, J., Ainsworth, S., Paul-Trifu, L., Davis, B., Xia, H., Napierala, E., Richardson, A., Baldwin, J., Chisnall, D., Clarke, J., Gudka, K., Joannou, A., Markettos, AT., Mazzinghi, A., Norton, RM., Roe, M., Sewell, P., Son, S., Jones, TM., Moore, SW., Neumann, PG. and Watson, RNM., Research data supporting 'Cornucopia: Temporal Safety for CHERI Heaps'
  • Xia, H., Woodruff, J., Ainsworth, S., Filardo, N., Roe, M., Richardson, A., Rugg, P., Neumann, P., Moore, S., Watson, R. and Jones, T., Research data supporting "CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety"
  • Theses / dissertations

  • Spliet, R., A SIMD architecture for hard real-time systems
  • Contact Details

    Room: 
    SC06
    Office phone: 
    (01223) 3-34657