Journal articles
Markettos, AT., Watson, RNM., Moore, SW., Sewell, P. and Neumann, PG., 2019. Inside risks through computer architecture, Darkly Communications of the ACM, v. 62
Doi: http://doi.org/10.1145/3325284
Markettos, AT., Watson, RNM., Moore, SW., Sewell, P. and Neumann, PG., 2019. Inside risks through computer architecture, Darkly Communications of the ACM, v. 62
Doi: 10.1145/3325284
Watson, RNM., Norton, RM., Woodruff, J., Moore, SW., Neumann, PG., Anderson, J., Chisnall, D., Davis, B., Laurie, B., Roe, M., Dave, NH., Gudka, K., Joannou, A., Markettos, AT., Maste, E., Murdoch, SJ., Rothwell, C., Son, SD. and Vadera, M., 2016. Fast Protection-Domain Crossing in the CHERI Capability-System Architecture IEEE Micro, v. 36
Doi: 10.1109/MM.2016.84
Woodruff, J., Joannou, A., Xia, H., Davis, B., Neumann, PG., Watson, RNM., Moore, S., Fox, A., Norton, R., Chisnall, D. and Fox, A., CHERI Concentrate: Practical Compressed Capabilities IEEE Transactions on Computers,
Doi: 10.1109/tc.2019.2914037
Conference proceedings
Chisnall, D., Davis, B., Gudka, K., Brazdil, D., Joannou, A., Woodruff, J., Markettos, AT., Maste, JE., Norton, R., Son, S., Roe, M., Moore, SW., Neumann, PG., Laurie, B. and Watson, RNM., 2017. CHERI JNI: Sinking the Java Security Model into the C OPERATING SYSTEMS REVIEW, v. 51
Doi: 10.1145/3037697.3037725
Markettos, AT., Moore, SW., Jones, BD., Spliet, R. and Gavrila, VA., 2016. Conquering the complexity mountain: Full-stack computer architecture teaching with FPGAs 2016 11th European Workshop on Microelectronics Education, EWME 2016,
Doi: http://doi.org/10.1109/EWME.2016.7496457
Fox, PJ., Markettos, AT. and Moore, SW., 2014. Reliably prototyping large SoCs using FPGA clusters 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014,
Doi: 10.1109/ReCoSoC.2014.6861350
Markettos, AT., Fox, PJ., Moore, SW. and Moore, AW., 2014. Interconnect for commodity FPGA clusters: Standardized or customized? Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014,
Doi: 10.1109/FPL.2014.6927472
Naylor, M., Fox, PJ., Markettos, AT. and Moore, SW., 2013. A spiking neural network on a portable FPGA tablet 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings,
Doi: http://doi.org/10.1109/FPL.2013.6645629
Naylor, M., Fox, PJ., Markettos, AT. and Moore, SW., 2013. Managing the FPGA memory wall: Custom computing or vector processing? 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings,
Doi: 10.1109/FPL.2013.6645538
Woodruff, J., Markettos, AT. and Moore, SW., 2013. A 64-bit MIPS processor running freebsd on a portable FPGA tablet 2013 23rd International Conference on Field Programmable Logic and Applications, FPL 2013 - Proceedings,
Doi: http://doi.org/10.1109/FPL.2013.6645630
Moore, SW., Fox, PJ., Marsh, SJT., Markettos, AT. and Mujumdar, A., 2012. Bluehive - A field-programable custom computing machine for extreme-scale real-time neural network simulation Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, FCCM 2012,
Doi: 10.1109/FCCM.2012.32
Markettos, AT. and Moore, SW., 2009. The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2009, PROCEEDINGS, v. 5747
Li, HY., Markettos, AT. and Moore, S., 2005. Security evaluation against electromagnetic analysis at design time CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2005, PROCEEDINGS, v. 3659
Li, HY., Markettos, AT. and Moore, S., 2005. Security evaluation against electromagnetic analysis at design time HLDVT'05: TENTH ANNUAL IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS,
Li, HY., Markettos, AT. and Moore, S., 2005. A security evaluation methodology for smart cards agnaist electromagnetic analysis 39TH ANNUAL 2005 INTERNATIONAL CARNAHAN CONFERENCE ON SECURITY TECHNOLOGY, PROCEEDINGS,
Filardo, N., Gutstein, BF., Woodruff, J., Ainsworth, S., Paul-Trifu, L., Davis, B., Xia, H., Napierala, ET., Richardson, A., Baldwin, J., Chisnall, D., Clarke, J., Gudka, K., Joannou, A., Markettos, AT., Mazzinghi, A., Norton, RM., Roe, M., Sewell, P., Son, S., Jones, TM., Moore, SW., Neumann, PG. and Watson, RNM., Cornucopia: Temporal Safety for CHERI Heaps Proceedings of the 41st IEEE Symposium on Security and Privacy,
Chisnall, DT., Davis, B., Gudka, K., Brazdil, D., Joannou, A., Woodruff, J., Markettos, AT., Maste, JE., Norton, R., Son, S., Roe, M., Moore, SW., Neumann, PG., Laurie, B. and Watson, RNM., CHERI JNI: Sinking the Java security model into the C Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems,
Woodruff, JD., Joannou, A., Kovacsics, R., Moore, SW., Bradbury, A., Xia, H., Robert, RNM., Chisnall, D., Roe, M., Davis, B., Napierala, E., Baldwin, J., Gudka, K., Neumann, PG., Mazzinghi, A., Richardson, A., Son, S. and Markettos, AT., Efficient Tagged Memory IEEE International Conference on Computer Design - VLSI in Computers and Processors,
Markettos, AT., Rothwell, C., Gutstein, BF., Pearce, A., Neumann, PG., Moore, SW. and Watson, RNM., Thunderclap: Exploring Vulnerabilities in Operating System IOMMU Protection via DMA from Untrustworthy Peripherals
Doi: 10.14722/ndss.2019.23194
David, B., Watson, R., Alexander, R., Peter, N., Moore, S., Baldwin, J., Chisnall, D., Clarke, J., Filardo, N., Gudka, K., Joannou, A., Laurie, B., Markettos, A., Maste, J., Mazzinghi, A., Napierala, E., Norton, R., Roe, M., Sewell, P., Son, S. and Woodruff, J., CheriABI: Enforcing Valid Pointer Provenance and Minimizing Pointer Privilege in the POSIX C Run-time Environment ACM,
Book chapters