The growing adoption of artificial intelligence (AI) across a wide range of applications is accompanied by a corresponding increase in model complexity, which introduces new challenges for deploying AI on edge devices with constrained memory, limited computational capacity, and strict energy requirements. Research efforts in this area are focused on both algorithmic and hardware optimization, often balancing accuracy against energy efficiency. At the algorithmic level, Hyperdimensional Computing (HDC) has emerged as a promising approach to either replace or complement conventional models such as deep neural networks, while processing-in-memory is increasingly recognized as a well-established strategy for hardware acceleration. In my work, I propose efficient hardware-software co-design methodologies and model optimizations that enable highly accurate edge AI while simultaneously enhancing computational efficiency. I demonstrate the effectiveness of hardware-aware ensembling methods for edge AI, highlighting their exceptional efficiency when integrating HDC learners. Furthermore, I exploit the significant parallelism inherent in HDC classifiers, co-designing them with analog memory arrays for processing-in-memory (PIM) acceleration.
Bio
Flavio Ponzina earned his M.Sc. degree in Computer Engineering from Politecnico di Torino, Italy, in 2018, and his Ph.D. degree in Electronic Engineering from EPFL, Switzerland, in 2023. He is currently a postdoctoral scholar at the University of California, San Diego (UCSD), La Jolla, CA, USA. His doctoral research focused on hardware-software co-design for energy-efficient edge AI, particularly through the integration of neural network-based ensembling methods with processing-in-memory (PIM) acceleration. At UCSD, he is expanding this work by exploring the co-optimization of hardware and software, with an emphasis on Hyperdimensional Computing (HDC), a brain-inspired computational paradigm, and emerging memory technologies.
