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Department of Computer Science and Technology

In Praise of Undergraduate Research

8 August 2019

In my last post I discussed the Janus automatic binary parallelisation tool that my postdoc, Kevin, has developed. At VEE earlier this year we had another paper on Janus , this time extending it to extract other forms of parallelism—automatic vectorisation for data-level parallelism and software prefetching for memory-level parallelism. We show how these schemes are applied to binaries in the context of Janus (with a neat trick for dealing with bounds-checking code when inserting prefetches to arrays) and evaluate them together. I’m not aware of any other work that tries to extract all three forms of parallelism at once. However, what I liked best about this paper was not the techniques, nor the results, but the fact that the two passes...

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Janus: Statically-Driven and Profile-Guided Automatic Dynamic Binary Parallelisation

18 February 2019

One of the themes of my research has been and continues to be the exploitation of parallelism in its many forms. I’ve looked into data-level parallelism by improving the performance of SLP by, for example, reducing the number of instructions that are vectorised and (spoiler alert for a future publication) I have a PhD student working on speculative vectorisation. With Sam Ainsworth , formerly my PhD student, now a postdoc, I have published research that exploits memory-level parallelism within the compiler , architecture and in both with a programmable prefetcher . We’ve also looked into taking advantage of parallelism for error detection . However, the first work I did in this area, and the kind of work...

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Parallel Error Detection Using Heterogeneous Cores

27 June 2018

Soft, or transient, errors are faults that occur seemingly at random, causing bits to flip within an integrated circuit. This is especially important in memory cells, and I remember very clearly reading a blog post from James Hamilton several years ago now, where he talked about the need for ECC on DRAM in servers and discussed some (what was then) recent academic work in the subject. ECC is a great way to protect memory, being high performance with low power and area overheads, given its ability to detect multiple errors and correct some too. However, beyond the memory hierarchy, techniques for error detection and recovery are little used due to the difficulties in protecting logic cheaply.

One area where error detection...

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World Cup 2018 Sticker Collecting

10 May 2018

Once again a major football tournament is approaching and my son is collecting stickers of all the teams who have reached the finals. This time it’s the World Cup in Russia and the album published by Panini has 682 to collect. I’ve blogged before about the maths behind collecting stickers so you can calculate how many packets of five distinct stickers you expect to need to finish it. At the time, to help me visualise this, I wrote a web page with a bit of JavaScript on it to do the calculations. This time I’ve looked over it again and increased its functionality a little, so I’ve decided it’s robust enough to advertise. It’s on my main university site...

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An Event-Triggered Programmable Prefetcher for Irregular Workloads

28 March 2018

Over the last few years my PhD student, Sam Ainsworth , and I have been looking into data prefetching, especially for applications containing irregular memory accesses. We published a paper in ICS 2016 about a specialised hardware prefetcher that optimises breadth-first traversals on graphs in the commonly-used compressed sparse-row format, which I previously blogged about . We also published a paper at CGO on automatic software-prefetch generation, more generally for indirect memory accesses ( blog post ). At ASPLOS this year, we marry the two ideas together and generalise even further, creating a programmable prefetcher, using an event-driven programming model, that is capable of fetching in data for many types of memory access, complete...

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Gonville and Caius

2 October 2017

Today I’m joining a college. Or, to be more precise, at a ceremony later this afternoon I’ll be admitted as a fellow to Gonville and Caius college .

Now the questions you might ask are why, and why aren’t you part of a college already—this is Cambridge after all and it’s all about the colleges, isn’t it?

Actually it’s not. In Cambridge you don’t have to be part of a college. All students are, both undergraduate and postgraduate. Postdocs generally aren’t, although some colleges make provision for a small number of postdocs to be part of their community. Lecturers, readers and professors can choose whether to be part of a college or not....

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Comparison of AArch64 Dynamic Binary Modification Tools

12 July 2017

Over the past few years I’ve become increasingly interested in dynamic binary modification (DBM) tools, so much so that I supervise a PhD student who is trying to parallelise binaries using one, and am just starting work on a grant that continues and extends this work . On Intel’s architecture, Pin is probably the most famous tool, and one that I had most experience of in the past. (As an aside, Pin is a dynamic binary instrumentation tool, but I’m going to use modification instead of instrumentation throughout this post, since modification subsumes instrumentation and I’m more interested in optimisation than just analysis.) However, it’s closed source and only targets Intel’s ISAs. Another option is ...

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Negar’s Memorial

7 June 2017

On Monday we held a memorial event in Emmanuel College for my PhD student, Negar , who died so tragically in October last year. These are the words I said in memory of her.

The first time I talked to Negar was just over 5 years ago, in May 2012. I can remember it vividly, sitting in Alan Mycroft’s office phoning Iran to interview a candidate for a job on hardware reliability. She came across as a quiet person who was unflustered by the questions that we threw at her. And behind that a determination too, a determination to secure the job, to come to Cambridge and achieve her ambition...

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Student Research Competition at EuroLLVM 2017

29 March 2017

My student, Sam Ainsworth , has won first prize in the student research competition at EuroLLVM 2017 . This work was previously published at CGO 2017 and I’ve blogged about it too. Below is a copy of his poster, or download it here . Well done, Sam!

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Software Prefetching for Indirect Memory Accesses

23 February 2017

I’ve always considered software prefetching to be something of a black art. There have been times in the past when I’ve looked at my code, noticed a load is causing problems and tried inserting one or more software prefetches to alleviate the issue. Mostly this hasn’t worked, although I’ve never been sure why. In fact, even when it has worked I haven’t been totally sure why it has, usually because it’s involved a lot of trial and error in trying out different options before I hit on improved performance.

Now it turns out that most of the time I was probably trying to prefetch the wrong things. Trying to prefetch linked data structures, which are those that involve pointer chasing (like a linked list),...

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My Year 2016

23 December 2016

I started blogging in October 2015 with the aim of publicising my group’s research a little more, having a space to write about topics and work that weren’t going to be published, and delving into our research results in more detail than possible in a page-constrained article. A year on, I wanted to look back and see how things had gone in my first year as a lecturer, but the events of this October overtook me. Now, at the end of the calendar year when everything is calmer, it seems like a good opportunity to summarise the last twelve months and point to blog posts written and events that I didn’t find time to talk about. Given the season I’ll try not to make it...

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Negar Miralaei

8 November 2016

It’s with immense sadness that I write about my PhD student, Negar Miralaei, who died in an accident back home in Iran on the 26th October. She will be sorely missed within my group and by everyone within the Computer Laboratory. Many tributes have been paid to her warmth, kindness and dedication to her research. You can read those from the Computer Lab and Varsity , for example.

Despite this being a short post, it has taken me nearly two weeks to write, such is the shock, sorrow and emptiness I have felt since being told the tragic news. Negar was a ray of sunshine in our group, always smiling, even in the face of adversity. She was...

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The Lynx Queue

9 August 2016

This post is about my group’s second ICS paper from June this year, which describes a new single producer / single consumer (SP/SC) software queue that we developed for frequent inter-core communication. It’s faster than existing implementations and we call it Lynx . It’s available on my group’s data page .

Initially, we didn’t set out to create a new queue. We were experimenting with transient error detection techniques in software. Transient, or soft, errors are faults that occur sporadically within a microprocessor, causing a data value or instruction to change. They are the result of strikes to the chip from cosmic rays (or usually the secondary particles they excite) or alpha particles from...

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Hardware Graph Prefetchers

3 June 2016

This week sees the publication of two papers from my research group at ICS 2016 and so, in this post, I’d like to look a little more into one of these schemes: the graph prefetcher that my student, Sam, has developed.

Graph workloads are important in a number of domains, and becoming increasingly so. You only have to look at the numerous social media applications to see examples of graph-based data (e.g. in a network of people, each person is a vertex and the edges represent links to friends). But graph representations are also significant in less publicly-visible application areas, such as those in scientific computing or “big data” analytics. However, efficient processing of graph workloads is often...

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Minute Madness on Program Parallelisation

25 May 2016

Today was the annual Wheeler lecture at the Computer Laboratory, and before the main event, a talk by Andrew Herbert, there was a Minute Madness where people from across the Lab, ranging from MPhil students through to professors, talked for one minute about their research with a single slide as a prop. My slide and something approximating the words I used are below.

“Hello! My group works on ways of making applications go faster, through a technique called program parallelisation.

If you look on the left of the slide, the red wavy arrow represents a regular sequential application with a single thread of execution within it. This means that instructions execute one...

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Panini FIFA Sticker Collections

14 March 2016

My eldest son likes collecting things. Of course all children seem to like picking up random objects and hoarding them forever, and we’ve had our fair share of leaves, stones, food wrappers and other assorted paraphernalia floating around the house until we can divert attention elsewhere and get rid of them. But my son also really likes collecting sets of toys, books and, currently, stickers.

He first got into this during the World Cup in 2014 when I thought he was old enough to really enjoy collecting the stickers of all the players and teams that you find in the famous Panini sticker album that’s published before each competition. I remember collecting these when I was growing up; the excitement at opening each pack...

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Alias Analysis in HELIX

21 December 2015

One of the most important parts of our HELIX compiler is the data dependence analysis we run on the compiler’s IR to determine which instructions are independent of each other. You can read more about HELIX in general in our original CGO 2012 paper (click through my publications page to get free access to the ACM version).

HELIX’s initial data dependence pass is split into two phases, and it’s the memory alias analysis stage that is most interesting. This has the job of identifying the locations in memory that are read and written by each instruction so that we can respect all data dependences within the loops we parallelise. Since alias analysis is not precise, we need to...

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Boosting Performance By Limiting Vectorisation

27 October 2015

It sounds a bit counter-intuitive, but boosting application performance by limiting the amount of vectorisation carried out is essentially what my postdoc, Vasileios Porpodas, and I have done in our latest paper on automatic vectorisation. We call it TSLP, or Throttled SLP, because it limits the amount of scalar code that the standard SLP algorithm converts into vectors.

The actual paper is available here . Vasileios presented it at PACT last week and will be at the LLVM Developers’ Meeting this week, so I thought it might be interesting to expand on one of the examples we give at the end, showing the source code and how it is actually vectorised with SLP and TSLP. The kernel is compute-rhs, which is a...

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Hello World!

1 October 2015

Today is the first day I’m officially employed as a University Lecturer , so it seems appropriate for my research blog to be born right now. It’s going to be a bit of an experiment (as you’d expect), but hopefully a place where I can describe the research my group is undertaking in more detail, in a different way to how it’s presented in our papers, and with interesting results that we don’t intend to publish in any conference or journal. My aim is to make the research more accessible and informal than our academic articles. Let’s see how I get on!

Cheers Tim

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Addressing Temporal Memory Safety

26 February 2020

Our upcoming Oakland paper was released onto the internet recently, despite the publication date actually being in May when the conference is held (the IEEE Symposium on Security and Privacy , to give its official name). So now seemed like a good time to talk about some of the security work we've been doing, in particular our research into schemes for temporal memory safety.

When we talk about memory safety, issues fall into two categories. The first, and most well-known, even if not by name, is spatial safety. This includes buffer-overflow vulnerabilities, such as the one that caused the infamous heartbleed bug . Here, during a TLS session, a missing check on the amount of data requested by...

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