skip to content

Department of Computer Science and Technology

Student Research Competition at EuroLLVM 2017

29 March 2017

My student, Sam Ainsworth , has won first prize in the student research competition at EuroLLVM 2017 . This work was previously published at CGO 2017 and I’ve blogged about it too. Below is a copy of his poster, or download it here . Well done, Sam!

Read more

Software Prefetching for Indirect Memory Accesses

23 February 2017

I’ve always considered software prefetching to be something of a black art. There have been times in the past when I’ve looked at my code, noticed a load is causing problems and tried inserting one or more software prefetches to alleviate the issue. Mostly this hasn’t worked, although I’ve never been sure why. In fact, even when it has worked I haven’t been totally sure why it has, usually because it’s involved a lot of trial and error in trying out different options before I hit on improved performance.

Now it turns out that most of the time I was probably trying to prefetch the wrong things. Trying to prefetch linked data structures, which are those that involve pointer chasing (like a linked list),...

Read more

Minute Madness on Program Parallelisation

25 May 2016

Today was the annual Wheeler lecture at the Computer Laboratory, and before the main event, a talk by Andrew Herbert, there was a Minute Madness where people from across the Lab, ranging from MPhil students through to professors, talked for one minute about their research with a single slide as a prop. My slide and something approximating the words I used are below.

“Hello! My group works on ways of making applications go faster, through a technique called program parallelisation.

If you look on the left of the slide, the red wavy arrow represents a regular sequential application with a single thread of execution within it. This means that instructions execute one...

Read more

Alias Analysis in HELIX

21 December 2015

One of the most important parts of our HELIX compiler is the data dependence analysis we run on the compiler’s IR to determine which instructions are independent of each other. You can read more about HELIX in general in our original CGO 2012 paper (click through my publications page to get free access to the ACM version).

HELIX’s initial data dependence pass is split into two phases, and it’s the memory alias analysis stage that is most interesting. This has the job of identifying the locations in memory that are read and written by each instruction so that we can respect all data dependences within the loops we parallelise. Since alias analysis is not precise, we need to...

Read more

Boosting Performance By Limiting Vectorisation

27 October 2015

It sounds a bit counter-intuitive, but boosting application performance by limiting the amount of vectorisation carried out is essentially what my postdoc, Vasileios Porpodas, and I have done in our latest paper on automatic vectorisation. We call it TSLP, or Throttled SLP, because it limits the amount of scalar code that the standard SLP algorithm converts into vectors.

The actual paper is available here . Vasileios presented it at PACT last week and will be at the LLVM Developers’ Meeting this week, so I thought it might be interesting to expand on one of the examples we give at the end, showing the source code and how it is actually vectorised with SLP and TSLP. The kernel is compute-rhs, which is a...

Read more