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I made the banner image for this blog to think about AI in Africa.

The red dunes of the Namib desert show the beauty of the African continent, and remind me of Nnedi Okorafor’s Binti . The cut-away behind the letters AI has been transformed using a Deep Neural Network for style transfer.

It's time to define some research priorities for our collaboration with Ethiopian colleagues.

Helen and I met with Tesfa Tegegne in Addis Ababa, to discuss issues relating to development of Amharic language resources in AI for Development, and potential for tools that might "leapfrog" data science methods and school curriculum for an AI generation.

Is it possible to teach and practice programming wholly in a national language, rather than the mix of English keywords and local content that is so typical of digital working?

Addisu Damena at the Bahir Dar Institute of Technology has created a system that does exactly this - not only for practical tasks like interactive websites, but even for experimenting with AI using neural networks.

The AI in Africa project has been covered in an interview on the BBC World Service programme Digital Planet.

In my last post I discussed the Janus automatic binary parallelisation tool that my postdoc, Kevin, has developed. At VEE earlier this year we had another paper on Janus , this time extending it to extract other forms of parallelism—automatic vectorisation for data-level parallelism and software prefetching for memory-level parallelism. We show how these schemes are applied to binaries in the context of Janus (with a neat trick for dealing with bounds-checking code when inserting prefetches to arrays) and evaluate them together. I’m not aware of any other work that tries to extract all three forms of parallelism at once. However, what I liked best about this paper was not the techniques, nor the results, but the fact that the two passes...

Soft, or transient, errors are faults that occur seemingly at random, causing bits to flip within an integrated circuit. This is especially important in memory cells, and I remember very clearly reading a blog post from James Hamilton several years ago now, where he talked about the need for ECC on DRAM in servers and discussed some (what was then) recent academic work in the subject. ECC is a great way to protect memory, being high performance with low power and area overheads, given its ability to detect multiple errors and correct some too. However, beyond the memory hierarchy, techniques for error detection and recovery are little used due to the difficulties in protecting logic cheaply.

One area where error detection...

Over the last few years my PhD student, Sam Ainsworth , and I have been looking into data prefetching, especially for applications containing irregular memory accesses. We published a paper in ICS 2016 about a specialised hardware prefetcher that optimises breadth-first traversals on graphs in the commonly-used compressed sparse-row format, which I previously blogged about . We also published a paper at CGO on automatic software-prefetch generation, more generally for indirect memory accesses ( blog post ). At ASPLOS this year, we marry the two ideas together and generalise even further, creating a programmable prefetcher, using an event-driven programming model, that is capable of fetching in data for many types of memory access, complete...

Over the past few years I’ve become increasingly interested in dynamic binary modification (DBM) tools, so much so that I supervise a PhD student who is trying to parallelise binaries using one, and am just starting work on a grant that continues and extends this work . On Intel’s architecture, Pin is probably the most famous tool, and one that I had most experience of in the past. (As an aside, Pin is a dynamic binary instrumentation tool, but I’m going to use modification instead of instrumentation throughout this post, since modification subsumes instrumentation and I’m more interested in optimisation than just analysis.) However, it’s closed source and only targets Intel’s ISAs. Another option is ...

My student, Sam Ainsworth , has won first prize in the student research competition at EuroLLVM 2017 . This work was previously published at CGO 2017 and I’ve blogged about it too. Below is a copy of his poster, or download it here . Well done, Sam!

I started blogging in October 2015 with the aim of publicising my group’s research a little more, having a space to write about topics and work that weren’t going to be published, and delving into our research results in more detail than possible in a page-constrained article. A year on, I wanted to look back and see how things had gone in my first year as a lecturer, but the events of this October overtook me. Now, at the end of the calendar year when everything is calmer, it seems like a good opportunity to summarise the last twelve months and point to blog posts written and events that I didn’t find time to talk about. Given the season I’ll try not to make it...

This post is about my group’s second ICS paper from June this year, which describes a new single producer / single consumer (SP/SC) software queue that we developed for frequent inter-core communication. It’s faster than existing implementations and we call it Lynx . It’s available on my group’s data page .

Initially, we didn’t set out to create a new queue. We were experimenting with transient error detection techniques in software. Transient, or soft, errors are faults that occur sporadically within a microprocessor, causing a data value or instruction to change. They are the result of strikes to the chip from cosmic rays (or usually the secondary particles they excite) or alpha particles from...

Today was the annual Wheeler lecture at the Computer Laboratory, and before the main event, a talk by Andrew Herbert, there was a Minute Madness where people from across the Lab, ranging from MPhil students through to professors, talked for one minute about their research with a single slide as a prop. My slide and something approximating the words I used are below.

“Hello! My group works on ways of making applications go faster, through a technique called program parallelisation.

If you look on the left of the slide, the red wavy arrow represents a regular sequential application with a single thread of execution within it. This means that instructions execute one...

One of the most important parts of our HELIX compiler is the data dependence analysis we run on the compiler’s IR to determine which instructions are independent of each other. You can read more about HELIX in general in our original CGO 2012 paper (click through my publications page to get free access to the ACM version).

HELIX’s initial data dependence pass is split into two phases, and it’s the memory alias analysis stage that is most interesting. This has the job of identifying the locations in memory that are read and written by each instruction so that we can respect all data dependences within the loops we parallelise. Since alias analysis is not precise, we need to...

Today is the first day I’m officially employed as a University Lecturer , so it seems appropriate for my research blog to be born right now. It’s going to be a bit of an experiment (as you’d expect), but hopefully a place where I can describe the research my group is undertaking in more detail, in a different way to how it’s presented in our papers, and with interesting results that we don’t intend to publish in any conference or journal. My aim is to make the research more accessible and informal than our academic articles. Let’s see how I get on!

Cheers Tim

Before starting the next leg of my fieldwork in Namibia, I made a side-trip to my home country of Aotearoa New Zealand, where Billie Lythberg, Rachel Wolfgramm and their colleagues have helped me to explore interpretations of AI in Maori and Pasifika cultures.

How do the Black Lives Matter protests relate to the AI in Africa project, and the work of Cambridge Global Challenges?