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Abstract: Custom hardware accelerators, such as FPGAs and ASICs, are a promising solution to deal with our increasing computational demands, as they offer high parallelism and energy efficiency. However, a major barrier to their success and adoption is the difficulty of hardware design--a task available exclusively to a limited number of hardware experts. In this talk, I will discuss the challenges and limitations of current hardware design approaches. I will outline hardware compilation techniques that overcome these limitations and make hardware design broadly accessible, fast, and reliable. Finally, I will share my vision for future advancements in hardware design and its accessibility to users from various application domains.
Bio: Lana Josipović is an Assistant Professor in the Department of Information Technology and Electrical Engineering at ETH Zurich. Prior to joining ETH Zurich in 2022, she received a Ph.D. in Computer Science from EPFL. Her research interests include reconfigurable computing and electronic design automation. She is a recipient of various research awards, including the EDAA Outstanding Dissertation Award, EPFL Doctorate Award, Google Ph.D. Fellowship in Systems and Networking, and Best Paper Awards at ISFPGA’20 and FPL’24. She is an Associate Editor for IEEE TCAD, ACM TRETS, and ACM TODAES, and served as general, program, and topic chair of several international conferences and workshops, including IWLS, FCCM, FPL, DAC, and DATE.
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