Building on Prof Watson's Wednesday seminar "15 years of the CHERI Research Project: Reflections, Current Work, and Next Directions", this talk will focus on the design and technology transition of CHERI security extensions for a range of instruction set architectures (ISAs) including ARM and RISC-V. Adding CHERI to a microprocessor core poses a number of microarchitectural design challenges that will be explored.
Simon Moore is a Professor of Computer Engineering at the University of Cambridge, Department of Computer Science and Technology, where he conducts research and teaching in the general area of computer architecture with a particular interest in secure and rigorously engineered processors and subsystems. He has led work on CHERI microarchitecture since the start of the CHERI project in 2010, and worked in collaboration with Prof Robert Watson and many others to bring CHERI research to where it is today.
Link to join virtually: https://cam-ac-uk.zoom.us/j/89473073451
This talk is being recorded. Any questions asked will also be included in the recording. The recording will be made available on the Department’s webpage
